Reliable optical communication systems require mechanisms for minimizing the effects of signal degradation occurring between associated transmitters and receivers. Signal degradation occurs due to a variety of factors that cannot be completely eliminated, and is exacerbated by the long-haul transmission distances and high optical channel counts required in many applications. Due to signal degradation, some transmitted data may be incorrectly interpreted at a receiver. If data is misinterpreted at a rate above that which is acceptable, the efficacy and viability of the system may be lost.
A variety of techniques for minimizing the effects of signal degradation have been investigated. Forward Error Correction (FEC) is one technique used to help compensate for signal degradation and provide “margin improvements” to the system. Margin improvements generally allow an increase in amplifier spacing and/or increase in system capacity. In a Wavelength Division Multiplexing (WDM) system, for example, margin improvements obtained through FEC techniques allow an increase in the bit rate of each WDM channel and/or a decrease the spacing between WDM channels. This translates directly into an increased system data capacity.
FEC typically involves insertion of a suitable error correction code into a transmitted data stream to facilitate detection and correction of data errors about which there is no previously known information. Error correction codes are generated in an FEC encoder for the data stream, and are sent to a receiver including an FEC decoder. The FEC decoder recovers the error correction codes and uses them to correct any errors in the received data stream.
Of course, the efficacy of FEC techniques is impacted by the ability of the optical signal receiver to correctly detect transmitted data and error correction codes. Improvements in receiver signal detection thus translate to improved performance of FEC codes in providing correction of bit errors. A known receiver configuration includes a decision circuit for converting the received data signal into a binary electrical signal, e.g. including logic ones and zeros representative of the transmitted data. The decision circuit may, for example, include a comparator for comparing the received data signal with a predetermined voltage level (the decision threshold). If the voltage level of the received data signal is above the decision threshold at a particular sample time, the comparator may output a logic one. If, however, the voltage level of the received data signal is below the decision threshold, the comparator may output a logic zero.
The decision circuit thus makes an initial decision as to the data bit values of the received data stream. The FEC decoder detects and corrects errors in the data stream established by the decision circuit. Certainly, therefore, optimal setting of the decision threshold in the decision circuit is important in achieving optimal system bit error rate (BER).
In a known configuration an optimal decision threshold is established by minimizing the total number of corrected errors reported by the FEC decoder. The total number of corrected errors is provided as feedback to a decision threshold control circuit which causes adjustment of the decision threshold to minimize the total number of corrected errors. A difficulty associated with this approach it that the direction of correction for the decision threshold is typically unknown. As such, the initial decision threshold correction may be implemented in an incorrect direction, resulting in an increase in the total number of corrected errors. The increase in errors may be corrected by the feedback loop in the next sample period, but is nonetheless inefficient.
Accordingly, there is a need for a method and apparatus for decision threshold control in an optical signal receiver, which is capable of efficiently controlling a decision threshold.